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11-117 11 transceivers preliminary product description ordering information typical applications features functional block diagram rf micro devices, inc. 7628 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com optimum technology matching? applied si bjt gaas mesfet gaas hbt si bi-cmos sige hbt si cmos 31 ifdgnd 29 resntr+ 28 resntr- 27 rshunt 26 do 25 vcc6 32 vcc7 30 vreg voltage regulator lo vco phase detector/ charge pump prescaler 16/17 synthesizer address 7 x2 tx data sync bt = 0.5 4mhz ico loop filter /4 1mhz phase detector / charge pump /4 filter appf lo chip control bdata1 10 mhz bpktctl bxtlen 500 khz 23 bnpwr 24 pllgnd 22 bdclk address 30 address 31 address 3 25-bit latch 16-bit shift register (read only) 25-bit shift register (write only) 21 bddata dbus 25 5 25 20 bnden 7 lpo 6 vcc4 5 vcc3 8 dvddh 4 rxin 3 txout 2 vcc2 1 vcc1 appf lo 1mhzif transmitter 60 mhz clock / data recovery receiver address 4 address 5 address 6 16 16 16 /2 500 khz 1mhz /6 /5 10 mhz 60 mhz /60 div r phase detector/ charge pump div r ref. osc. 19 osc i 18 osc o 17 brclk lpf/ equalizer 9 iref 10 vcc5 11 d1 12 bpktctl 13 bdata1 14 recclk 15 recdata 16 bxtlen 12 mhz rx data tx data fsk demodulator rx data tx data RF2968 bluetooth tm transceiver ? bluetooth gsm/gprs/edge cellular phones bluetooth wireless lan cordless phones battery-powered portable devices the RF2968 is a monolithic integrated circuit intended for use as a low-cost fsk transceiver in bluetooth applica- tions. the device is provided in 32-lead plastic lpcc packaging and is designed to provide a fully-functional fsk transceiver. the chip is intended for bluetooth appli- cations in the 2.4ghz to 2.5ghz ism band. the if and demodulation sections of the chip require no external fil- ters or discriminators. the chip also features an image reject front end and a fully programmable synthesizer with integrated oscillator circuitry. self-calibrating rx and tx if circuitry optimizes link performance and eliminates manufacturing variations. bluetooth is a trademark owned by the bluetooth sig, inc., and licensed to rf micro devices, inc. fully monolithic integrated transceiver self-calibrating transceiver image reject receiver bluetooth and bluerf compatible supports reference clocks to 40mhz smallest footprint bluetooth transceiver tbd 11 rev a13 010912 notes: 1. shaded lead indicates pin 1. 2. package surface roughness at 1.5 m0.30. 0.70 0.08 5 m-20 m 1.00 max detail a -c- 1.0 max 11 1 (4x) 0.50 0.70 0.08 see detail a seating plane -c- 4.75 0.10 -b- 0.20 0.40 0.10 5.00 0.10 4.75 0.10 -a- 5.00 0.10 package style: lcc, 32-pin, 5x5
preliminary 11-118 RF2968 rev a13 010912 11 transceivers absolute maximum ratings parameter ratings unit supply voltage -0.5 to +3.6 v dc control voltages -0.5 to v cc v dc input rf level +10 dbm operating ambient temperature -40 to +85 c storage temperature -55 to +125 c parameter specification unit condition min. typ. max. overall t=25 c, v cc =3.0v rf frequency range 2400 to 2500 mhz vco and pll section vco frequency range 1100 to 1350 mhz frequency tolerance -50 50 khz 20ppm crystal; -40c to +85c rf channels 79 step size 1 mhz freq=2.4ghz ssb phase noise -90 dbc/hz freq=2.4ghz, 500khz offset -110 dbc/hz freq=2.4ghz, 2mhz offset -124 dbc/hz freq=2.4ghz, 3mhz offset reference frequency 10 13 20 mhz 10, 11, 12, 13, 20mhz 20 26 40 mhz div2enb=0; 20, 22, 24, 26, 40mhz. hop time 130 175 s dual bw=75khz and 25khz; bw switch delay=100 s k vco 85 mhz/v vco freq=1.2ghz transmit section data rate 1 mbps output power 0 4 dbm power control range 28 db power control step size 4 db gain step switching time 4 s from -28db to 0db output impedance 25 50 100 ? vswr<2:1 deviation 140 160 175 khz peak, data sequence 00001111 115 khz peak, data sequence 01010101 transmit isi data sequence 1010 min freq dev, % eye open 80 100 % reference data sequence 00001111 zero crossing error -125 125 ns + 1/8 symbol in-band spurious measurement bw=100khz adjacent channel power -20 dbc second channel power -20 dbm > third channel power -40 dbm out-of-band spurious measurement bw=100khz operation -36 dbm 30mhz to 1ghz -30 dbm 1ghz to 12.75ghz -47 dbm 1.8ghz to 1.9ghz -47 dbm 5.15ghz to 5.3ghz idle -57 dbm 30mhz to 1 ghz -47 dbm 1ghz to 12.75 ghz -47 dbm 1.8ghz to 1.9ghz -47 dbm 5.15ghz to 5.3ghz caution! esd sensitive device. rf micro devices believes the furnished information is correct and accurate at the time of this printing. however, rf micro devices reserves the right to make changes to its products without notice. rf micro devices does not assume responsibility for the use of the described product(s).
preliminary 11-119 RF2968 rev a13 010912 11 transceivers parameter specification unit condition min. typ. max. overall receive section cascaded voltage gain 18 64 db cascaded noise figure 8 db cascaded input ip 3 -14 dbm rx sensitivity -85 dbm if bw=1mhz, ber=10 -3 image rejection 30 db rx input impedance 25 50 100 ? 2:1 vswr max. interference performance ber <10 -3 (c=desired signal/i=interferer) co-channel interference, c/i co-channel 14 db c=-60dbm adjacent (1mhz) interference, c/i 1mhz +4 db c=-60dbm adjacent (2mhz) interference, c/i 2mhz -30 db c=-60dbm adjacent (> 3mhz) interfer- ence, c/i > 3mhz -40 db c=-67dbm image frequency interfer- ence, c/i image -9 db c=-67dbm adjacent (1mhz) interference to in-band image, c/i image+ 1mhz -20 db c=-67dbm out-of-band blocking ber <10 -3 , c=-67dbm, tested per evalua- tion board schematic interfering signal frequency 30mhz to 2000mhz -10 dbm 2000mhz to 2400mhz -27 dbm 2500mhz to 3000mhz -27 dbm 3000mhz to 12.75ghz -10 dbm intermodulation characteristic ber <10 -3 (bt= bluetooth modulated signal) f1, f2 -39 dbm f0=-64dbm bt signal f1=sine f2=bt signal |f2-f1|=3mhz, 4mhz or 5mhz f0=2f1-f2 maximum usable level -20 dbm ber <10 -3 spurious emissions measurement bw=100khz 30mhz to 1ghz -57 dbm 1ghz to 12.75ghz -47 dbm rssi operating range -80 -20 dbm power level at rx in pin rssi resolution 1 db rssi absolute accuracy -4 4 db -60dbm input power front end voltage gain 25.5 27.5 29.5 db power gain 20 db noise figure 6 8.5 db iip3 -14 dbm if section if frequency 1 mhz voltage gain -9.5 37 db followed by 1 bit a/d noise figure 25 db
preliminary 11-120 RF2968 rev a13 010912 11 transceivers parameter specification unit condition min. typ. max. data voltages z load >10k ? logic low 0.3 v logic high v cc -0.3 v power supply voltage 2.5 3.3 3.6 v tx current consumption 49 ma transmit mode, +4dbm output power rx current consumption 49 ma receive mode sleep modes 1 a sleep mode, no low power clock 250 a sleep mode, low power clock, 12mhz refer- ence 750 a sleep mode, low power clock, other refer- ence
preliminary 11-121 RF2968 rev a13 010912 11 transceivers pin function description interface schematic 1vcc1 supply voltage for the vco doubler and lo amplifier circuits. 2vcc2 supply voltage for the rx mixers, tx pa, and lna bias circuits. 3txout transmitter output. tx out output impedance is 50 ? (nominal) when the transmitter is enabled. tx out is a high impedance when the transmitter is disabled. because this pin is dc-biased, an external cou- pling capacitor is required. 4rxin receiver input. rx in input impedance is a low impedance when the receiver is enabled. rx in is a high impedance when the receiver is disabled. an internal series inductor is used to tune the input imped- ance. 5vcc3 supply voltage for the rx input stage (lna). 6vcc4 supply voltage for the tx mixers and bias circuits of the lo amplifier, lna, and rx mixers. 7lpo low frequency clock output for low power mode. in sleep mode, this pin may provide either a 3.2khz or 32khz clock having a 50% duty cycle to the baseband. in other modes, the output is disabled. 8dvddh supply voltage for the rx if vga circuit. 9iref connects an external precision resistor (1% tolerance) for generation of a constant current reference. 10 vcc5 supply voltage for the analog if circuits. 11 d1 this is the output of the charge pump for clock recovery circuit. a rc network from this pin to ground is used to establish the pll bandwidth. see pin 26. 12 bpktctl in transmit mode, this pin is used as a strobe to enable the pa stage. in receive mode, the baseband has the option to use this pin to signal the detection of the sync word. the baseband drives this pin high at the end of the sync word, at which time a second dc estimation is per- formed by sampling the trailer bits. if baseband control is not desired to signal the second dc estimation, then an internal timer is used to mark the end of the sync word. the bbc bit is used to select the baseband control option; the default setting uses the internal timer. see pin 23. 13 bdata1 input data to transmitter/output data from receiver. the input data is unfiltered data at 1mhz data rate. the pin is bidirectional, switching between data in and data out modes during transmit and receive modes respectively. 14 recclk recovered clock output. see pin 17. 15 recdata recovered data output. see pin 17. 16 bxtlen this pin is part of the chip power control circuit. it is used to enable/dis- able ?sleep? mode of chip. tx out 10 ? v cc rx in v cc3 vcc3 rxdata tx data bdata1 bxtlen v cc
preliminary 11-122 RF2968 rev a13 010912 11 transceivers pin function description interface schematic 17 brclk reference clock output. this is a crystal controlled reference clock in the 10-40mhz range, typically 13mhz. 18 osc o same as pin 19. see pin 19. 19 osc i the osc pins are used to produce the reference frequency by means of negative feedback. a crystal and resistor are placed in parallel from osc i to osc o to provide the feedback path and establish the reso- nant frequency. a shunt capacitor is placed on each osc pin to provide the proper loading of the crystal. if an external reference is used, it is connected to osc i through a dc-blocking capacitor, and osc o is connected to osc i through a 470k ? resistor. 20 bnden latches data entered into the serial port. data is clocked into the latch on the rising edge of bnden. see pin 23. 21 bddata serial data port. read/write data is sent through this pin into / out of the on chip shift register. read data is transferred on the rising edge of bdclk. write data is transferred on the falling edge of bdclk. 22 bdclk serial port input clock.this pin is used to clock data into the serial port. to minimize the hop frequency programming time, a bdclk frequency of 10-20mhz is recommended. see pin 23. 23 bnpwr this pin is part of the chip power control circuit. it is used to power up the chip from the ?off? state. 24 pll gnd ground connection for the rf synthesizer, crystal oscillator, and serial port. 25 vcc6 supply voltage for the rf synthesizer, crystal oscillator, and serial port. 26 d0 this is the output of the charge pump for the rf pll. an rc network from this pin to ground is used to establish the pll bandwidth. to mini- mize synthesizer settling time and phase noise, a dual loop bandwidth scheme is implemented. during the initial period of frequency acquisi- tion, a wide loop bandwidth is used. rshunt is used to switch to a narrow loop bandwidth near the end of the frequency acquisition, pro- viding improved vco phase noise. the time at which the bandwidth switches is set by the plldel bits. 27 rshunt switches the loop filter from wide to narrow bandwidth by shunting the midpoint of two external series resistors to ground. 28 resntr- the resntr pins are used to supply dc voltage to the vco as well as to tune the center frequency of the vco. two inductors are required between resntr- and resntr+ to resonate with the internal capac- itance. inductance of traces from the resntr pins to the inductor should be taken into account in the board layout. v cc brclk osc o osc i read data write data pin 21 bnpwr v cc d0 v cc resntr- resntr+ d0 4k ?
preliminary 11-123 RF2968 rev a13 010912 11 transceivers pin function description interface schematic 29 resntr+ see pin 28. 30 vreg voltage regulator output (2.2v). a bypass capacitor from this pin to ground is required. this voltage is used to bias the vco through the tank circuit tied to pins 28 and 29. 31 ifdgnd ground connection for the digital if circuits. 32 vcc7 supply voltage for the digital if circuits. esd this diode structure is used to provide electrostatic discharge protec- tion to 3kv using the human body model. the following pins are pro- tected: 6-7, 9-17, 20-27, 30-32. die flag gnd ground connection for all circuits other than those grounded through dedicated pins. the die flag must be connected to the ground plane with very low inductance for best performance. vreg v cc v cc
preliminary 11-124 RF2968 rev a13 010912 11 transceivers theory of operation the RF2968 is the first in a family of 2.4ghz transceivers developed specifically for bluetooth applications. it operates as a power class 2 (+4dbm) or class 3 (0dbm) bluetooth device and is fully compliant to version 1.0b of the bluetooth radio specification. for power class 1 (+20dbm) applications, the RF2968 may be used with a power amplifier such as the rf2172. processed in 0.35um silicon bi-cmos and packaged in a 5mm-square, industry-standard 32-pin leadless plastic package, the RF2968 provides high performance at a very low cost. with integrated if filtering, the RF2968 requires minimal external components and eliminates the need for costly components such as if saw filters and baluns. the high impedance 'off' states of the receiver input and transmitter output also eliminate the need for an external trans- mit/receive (t/r) switch. a complete bluetooth solution may be implemented with the RF2968 in conjunction with an antenna, rf bandpass filter, and baseband controller. in addition to the rf signal processing, the RF2968 also performs the baseband functions of data demodulation, dc compensation, and data and clock recovery while access code corre- lation takes place in the baseband device. the RF2968 transmitter output is internally matched to 50 ? , and requires an ac-coupling capacitor. the receiver's low noise amplifier (lna) input ( rxin pin) is internally matched to present a 50 ? impedance to the front end filter. a single front end filter may be shared by the transmitter and receiver by simply connecting the txout coupling capacitor to rxin . alternatively, the transmit path may be externally amplified to +20dbm, which, in conjunction with the RF2968?s transmit gain control and received signal strength indicator (rssi), allows bluetooth -compliant operation for power class 1. the rssi data is accessed via the serial port and provides a 1db resolution over the rx input power range of -20to- 80dbm. transmit gain control is adjustable in 4db steps and is also set via the serial port. baseband data is sent to the transmitter via the bdata1 pin, which is a bidirectional pin, acting as an input in transmit mode and an output in receive mode. the RF2968 performs the gaussian filtering of the baseband data, fsk-modulates the if current controlled oscillator (ico), and upconverts the if to the rf channel frequency. the on-chip voltage controlled oscillator (vco) is frequency synthesized to one half of the required local oscillator (lo) frequency and then doubled to produce the correct lo frequency. two external tank inductors between resntr+ and resntr- set the tuning range of the vco. voltage is supplied to the vco from an on-chip regulator that is connected to the midpoint of the two tank inductors through a filtering network. due to the fast frequency hopping requirements of bluetooth , the loop filter components (connected to pins d0 and rshunt ) are especially critical as they largely deter- mine the hopping and settling time of the vco. use of the component values as given in the application schematic is strongly recommended. the RF2968 may use either a 10mhz, 11mhz, 12mhz, 13mhz, or 20mhz reference clock frequency and can also sup- port a reference clock at double these frequencies to provide a migration path toward smaller end-product designs. this clock may be supplied by an external reference applied directly to osc i through a dc-blocking capacitor. if an external reference is not available, then a crystal and two capacitors may be used to complete the reference oscillator circuitry contained on-chip. for either an externally or internally generated referenced frequency, a resistor between osc i and osc o is required for proper biasing. the frequency tolerance of the reference clock must be 20ppm or better to assure that the maximum allowed system frequency error remains within the demodulation bandwidth of the RF2968. a select- able 3.2khz or 32khz low power mode clock is available at the lpo pin to supply the baseband device with a low fre- quency clock in sleep mode. where minimal sleep mode power consumption is a concern and reference clock frequency selection is flexible, a 12mhz reference clock should be chosen. the receiver uses a low-if architecture to minimize external component count. the rf signal is downconverted to 1mhz, allowing if filtering to be incorporated on chip. demodulated data is output at the bdata1 pin. further data pro- cessing is performed by the data and clock recovery circuitry, which utilizes a baseband pll. pin d1 istheloopfiltercon- nection for the baseband pll. the synchronized data and clock are output at pins recdata and recclk .ifthe baseband device used with the RF2968 performs the clock recovery, then the d1 loop filter components may be omitted. the interface between the RF2968 and baseband device is described in the 'application information' section of the full- length datasheet available from the rfmd web site (www.rfmd.com).
preliminary 11-125 RF2968 rev a13 010912 11 transceivers detailed functional block diagram pin out 31 ifdgnd 29 resntr+ 28 resntr- 27 rshunt 26 do 25 vcc6 32 vcc7 30 vreg lo vco phase detector/ charge pump prescaler 16/17 synthesizer address 7 x2 tx data sync bt = 0.5 4mhz ico loop filter /4 1mhz phase detector / charge pump /4 filter appf lo chip control bdata1 10 mhz bpktctl bxtlen 500 khz 23 bnpwr 24 pllgnd 22 bdclk address 30 address 31 address 3 25-bit latch 16-bit shift register (read only) 25-bit shift register (write only) 21 bddata dbus 25 5 25 20 bnden 7 lpo 6 vcc4 5 vcc3 8 dvddh 4 rxin 3 txout 2 vcc2 1 vcc1 appf lo 1mhzif transmitter 60 mhz clock / data recovery receiver address 4 address 5 address 6 16 16 16 /2 500 khz 1mhz /6 /5 10 mhz 60 mhz /60 div r phase detector/ charge pump div r ref. osc. 19 osc i 18 osc o 17 brclk lpf/ equalizer 9 iref 10 vcc5 11 d1 12 bpktctl 13 bdata1 14 recclk 15 recdata 16 bxtlen 12 mhz rx data tx data fsk demodulator rx data tx data 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 vcc7 31 ifdgnd 30 vreg 29 resntr+ 28 resntr- 27 rshunt 26 do 25 vcc6 8 7 6 5 4 3 2 1 iref vcc5 d1 recclk recdata bpktctl bdata1 bxtlen pll gnd bnpwr bdclk bddata bnden osc i osc o brclk dvddh lpo vcc4 vcc3 rx in tx out vcc2 vcc1
preliminary 11-126 RF2968 rev a13 010912 11 transceivers application schematic for typical gsm handset (assumes clock recovery performed by baseband) 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bxtlen bdata1 22 nf* 22 nf* lpo 20 k ? 1% 22 nf* bpktctl brclk 1nf 22 nf* 330 pf 20 k ? 30 pf 3.9 nh 1 f 820 ? 1 f *note: required supply filtering may vary depending on implementation. bnden bddata bdclk bnpwr 3.9 nh 43 k ? 470 k ? 22 nf fl1 v cc v cc v cc ref in v cc
preliminary 11-127 RF2968 rev a13 010912 11 transceivers evaluation board schematic (download bill of materials from www.rfmd.com.) 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bxtlen bdata1 recclk recdata c1* 22 nf vcc c3* 22 nf lpo r1 20 k ? 1% c4* 22 nf c6 2.7 nf r2 22 k ? c5 100 pf bpktctl brclk c8 47 pf y1 13 mhz c9* 22 nf c11 330 pf r4 20 k ? c10 30 pf l2 3.9 nh c12 1 f r6 820 ? c13 1 f *note: required supply filtering may vary depending on implementation. vcc bnden bddata bdclk bnpwr vcc vcc p1 con20 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bdclk bddata bnden brclk vcc bxtlen recdata recclk bpktctl bnpwr bdata1 vcc lpo l1 3.9 nh r5 43 k ? r3 470 k ? c7 47 pf c2 22 nf fl1 rx in/tx out
preliminary 11-128 RF2968 rev a13 010912 11 transceivers application information baseband interface the RF2968 rf transceiver serves as the physical layer (phy) in a bluetooth system and supports the bluerf interface between phy and baseband devices. the RF2968 contains the data demodulation, dc compensation, and data and clock extraction circuitry while the access code correlator function takes place in the baseband. there are two interfaces between the RF2968 and the baseband. the serial interface provides the path for control data exchange, and the bidirectional interface provides the path for modem, timing, and chip power control signals. figure 1 shows bidirectional signals with arrowheads on both ends of the line. serial interface control data is exchanged between the RF2968 and the baseband by means of the dbus serial interface protocol. bdclk , bddata ,and bnden are the signals comprising the serial interface. the baseband is the master device, initi- ating all accesses to the RF2968 registers. the data registers of the RF2968 are programmed or recalled according to the specified command format and address assignments. data packets are transmitted msb first. serial data packet format during a write, the baseband drives out each bit of the packet on the falling edge of bdclk . the RF2968?s data register is updated with the shift register contents on the first falling edge of bdclk after bnden is driven high. see figure 2. field number of bits comments device address 3 [a7:a5] ?101? for phy read/write 1 [r/w] ?1?=read, ?0?=write register address 5 [a4:a0] maximum of 32 registers data 16 [d15:d0] the RF2968 is programmed in write mode and returns its register contents in read mode. spi slave bidirectional interface RF2968 spi master bidirectional interface baseband bdata1 bpktctl bxtlen bnpwr brclk bddata bdclk bnden figure1. baseband/RF2968 interface bdclk . .. bnden ... d15 d14 a6 a5 a3 a2 a1 a0 a7 a4 d1 d2 d0 a6 a7 don't care bddata r/w = write = 0 figure 2. dbus write programming diagram
preliminary 11-129 RF2968 rev a13 010912 11 transceivers in a read operation, the baseband sends the device address, read bit (r/w = 1), and register address to the RF2968 followed by a ?turn-around? bit which lasts half a clock cycle. this turn-around allows the RF2968 to drive its requested data, via bddata , on the rising edges of bdclk . following the transfer of the last data bit (d[0]), the baseband drives bnden high and resumes control of bddata on the falling edge of the first bdclk pulse after bnden is driven high. seefigure3. register definition the register address field allows up to 32 registers for various functions. the RF2968 implements only register addresses 3-7 and 30-31. register 3 - if register 1 (read-only) bit number bit name comments 7 - 15 n/a not assigned 0 -6 rssi[6:0] the rssi value indicates the average power measured during the first 10 s after a packet has been detected. the baseband reads this register to obtain the current received signal strength indicator measurement. the rssi value may range from 0dbm to -127dbm in 1db increments. (all 0?s indicates 0dbm; all 1?s indicates -127dbm.) the rssi circuitry is designed to operate from -20dbm to -80dbm with an accuracy of 4db at -60dbm. example: rssi[6:0]=[110101] indicates -53dbm. bdclk bnden slave driving bddata master driving bddata ... ... d15 a6 a5 a3 a2 a1 a0 a7 a4 d1 d2 d0 a6 a7 bddata don't care turn-around turn-around r/w = read = 1 d14 floating floating figure 3. dbus read programming diagram
preliminary 11-130 RF2968 rev a13 010912 11 transceivers register 4 - if register 2 (write-only) lpo [1:0]: tdet [1:0]: bit number bit name comments 12-15 n/a not assigned 11 chopenb enables circuitry that significantly reduces the levels of rf pll comparison frequency spurious responses. 1: spur cancellation disabled. 0: normal mode. spur cancellation enabled. 10 div2enb enables an additional divide-by-two operation in the reference divider cir- cuitry to accommodate the use of a 20mhz-40mhz crystal or clock. this allows a migration path to higher reference frequencies. 1: normal mode. 10, 11, 12, 13, or 20mhz reference clock. 0: expanded mode. reference clock is double that allowed in normal mode. 8-9 lpo[1:0] determines the function of the low power mode clock (output at pin 7) when the device is in sleep mode according to the table below. in non-sleep modes, the output is disabled. 5-7 gain[2:0] sets the gain of the transmitter path. the gain is normally programmed immediately after the register write to enter the wait data sync state in power class 1 applications. gain is adjustable from 0dbto-28db in 4db steps. [all 0?s indicates high gain (0db attenuation); all 1?s indicates low gain (28db attenuation).] example: gain[2:0]=[011] indicates 12db attenuation. 4 enslowagcb 1: slow agc disabled. 0: normal mode. slow agc enabled. 3 n/a not assigned 2 tpl_ac selects a path in the rx data dc estimation circuit. 1: selects the dc estimation path that is ac coupled and which is normally used for the payload part of packet. 0: selects the fast dc estimation rx data path normally used for the access code of packet. 0-1 tdet[1:0] sets the receiver gain according to the table below. lpo[1:0] output at lpo (pin 7) 0x 32khzclock 1 0 3.2khz clock 1 1 clock disabled tdet[1:0] vga gain (db) filter gain (db) total gain (db) step size (db) 11 -11 1.5 -9.5 10 4.5 1.5 6.0 15.5 01 4.5 17 21.5 15.5 00 20 17 37.0 15.5
preliminary 11-131 RF2968 rev a13 010912 11 transceivers register 5 - if register 3 (write-only) bit number bit name comments 15 bypasssm selects or bypasses the state machine. 1: bypass mode. internal power-up signals can be directly controlled by programming of the respective bits in this register [0:3, 6:7]. 0: normal mode. all internally controlled power-up signals are derived from the state machine. 14 bbc selects baseband control or internal timer control for determining the time at which to perform dc estimation on the trailer bits. 1: baseband control. the baseband drives bpktctl high at the end of the sync word. 0: internal timer control. 13 n/a not assigned. 12 test if test mode enable. used only in ic verification; not for use in end product. 1: if test mode 0: normal mode 11 calrxvga calibration which compensates for the gain of the lna, mixer, and vga. see ?special modes: cal- ibration?. 10 cal_tx_pll calibrates the k 0 (gain of the current controlled oscillator) of the tx pll and, by nature of the design, calibrates the k 0 of the rx pll. see ?special modes: calibration?. 9 cal_gauss_cell calibration which compensates for the offset and the amplitude of the gaussian tx data that mod- ulates the tx pll ico. see ?special modes: calibration?. 8 loopback 1: loopback mode. the tx if output is looped back to the rx if input. 0: normal mode 7 pu_xtal powers up the crystal oscillator circuitry. see ?bypasssm? bit. 1: power on 0: power off 6 pu_mult powers up the frequency multiplier for the fm demodulator clock. see ?bypass sm? bit. 1: power on 0: power off 5 calrxfil calibrates the channel filter, demodulator low pass filter, and ac coupling filter in the dc estima- tion circuit in the receiver, as well as the gaussian filter and gfsk harmonic filter in the transmit- ter. see ?special modes: calibration?. 4 calrxpll_int calibration which compensates for the offset of the rx data path in the rx pll interface circuit. see ?special modes: calibration?. 3 pu_pa powers up the transmit output amplifier. see ?bypasssm? bit. 1: power on 0: power off 2 pu_rx powers up all receiver and synthesizer circuits. see ?bypasssm? bit. 1: power on 0: power off 1 pll_bw selects the loop bandwidth of the rf pll by controlling the state of the rshunt pin. under state machine control, this switch is executed according to the setting of the plldel[1:0] bits. 1: narrow bandwidth. rshunt is short-circuited to ground. 0: wide bandwidth. rshunt is a high impedance. 0 pu_tx powers up all transmitter and synthesizer circuits except for the output amplifier. see ?bypasssm? bit. 1: power on 0: power off
preliminary 11-132 RF2968 rev a13 010912 11 transceivers register 6 - if register 4 (write-only) register 7 - pll control (write-only) plldel [1:0]: divr [2:0]: bit number bit name comments 0-15 n/a not assigned bit number bit name comments 15 set_tx_pll_lf_ext configures the lpo pin as a test pin when bits lpo[1:0] are set high. 1: test mode. lpo is connected to the if pll loop filter of the transmitter. (see ?special modes: transmitter test mode?.) 0: normal mode. lpo is not connected to the if pll loop filter of the trans- mitter. 13 - 14 plldel [1:0] determines the time in which the pll remains in high bandwidth mode before switching to low bandwidth mode. in high bandwidth mode, the pll loop bandwidth is optimized for fast frequency locking. in low bandwidth mode, the loop bandwidth is optimized for low phase noise. see below. see also pin descriptions of d0 and rshunt, and bit pll_bw (register 5, bit 1). 12 rssi_test configures the rssi circuitry to operate continuously for test purposes. 1: test mode. continuous operation. 0: normal mode. packet-based operation. 9 - 11 divr [2:0] selects the external crystal frequency. see below. 8 tx_en powers up the tx voltage and current bias circuits and the tx pll?s ico voltage threshold set circuit. 7 rx_en powers up the rx voltage and current bias circuits. 0 - 6 pll [6:0] sets the rf pll frequency. see below. plldel [1:0] delay (us) 00 0 01 50 10 100 11 150 divr [2:0] crystal freq (mhz) 011 12 100 10 101 11 110 13 111 20
preliminary 11-133 RF2968 rev a13 010912 11 transceivers pll[6:0]: these bits determine the local oscillator (lo) frequency (i.e., the frequency at the doubler output) for both rx and tx modes. the lo frequency is set 1mhz above the channel center frequency. the pll [6:0] data bits represent the fre- quency offset (f offset ) in mhz from a base frequency of 2400mhz. for the normal bluetooth frequency range of 2402mhz to 2480mhz, f offset will range from 3 to 81; for the optional extended bluetooth range (up to 2497mhz), f offset will range from 3 to 98 (high-side injection assumed in both cases). example: assume a channel frequency of 2448mhz. the lo frequency is then: 2448+1=2449mhz, and f offset is: 2449-2400= 49. pll [6:0] is then:0110001 register 30 - manufacturer?s id code lsb?s (read-only) register 31 - manufacturer?s id code msb?s (read-only) bidirectional interface data exchange and timing all bidirectional timing may be derived from brclk , which is generated by the RF2968. the RF2968 uses the falling edges of brclk , and the baseband uses the rising edges. figure 4 shows the general timing for the case of data being transferred from the RF2968 to the baseband. state machine control the chip control circuitry of the RF2968 places the device into the required transmit, receive or power saving mode by controlling the power down and reset states of all other circuits in the device. the chip control inputs come from the baseband device ( bnpwr , bxtlen , bpktctl , bdata1 ) via the bidirectional interface and from the registers at the output of the dbus block ( rxen , txen ). state machines in the baseband and the RF2968 maintain the state which con- trols the direction of the bidirectional lines. the baseband controls the state machine in the RF2968 and ensures that data contentions do not occur during reset and normal operation. the control of individual sections of the RF2968 in each state is as follows. bit number bit name comments 0 - 15 id_code [15:0] lower 16 bits of manufacturer?s code. the fixed ?1? lsb of the manufacturer code is read at bit 0. bit number bit name comments 0 - 15 id_code [31:16] upper 16 bits of manufacturer?s code. the msb of the version number is read at bit 15. the RF2968 code is hex10b9825d. brclk bb data sampling points bdata1 figure 4. general bidirectional timing (RF2968 writing to baseband)
preliminary 11-134 RF2968 rev a13 010912 11 transceivers state description off all circuits are powered down and reset; configuration data is lost. (clrb=0) pwron wait xtl reset is released (clrb=1) and the oscillator is turned on (pdxtal=1). hold xtl this mode is entered when the oscillator has settled. configuration data can be read through the dbus inter- face. idle this is a standby mode. data can be read into the control registers (through the dbus) and the oscillator remains on. all other circuits are powered down. sleep the device normally enters this mode from idle, in which case every circuit is powered down but not reset, so that configuration data is retained. the device may also enter this mode from any other except pwron wait xtl or hold xtl, but the txen and rxen functions are not overridden, so that tx and rx circuits may remain on. wait xtl the oscillator is turned on (pdxtal=1) and allowed to settle before returning to idle mode. wait data sync this is the start of the transmit sequence. this mode is entered by the baseband writing to the control registers (through the dbus). when this happens, txen goes high, turning on the synthesizer and initializing a fixed delay, after which all the transmit circuits (except for the pa) are turned on (pd_tx=1). the baseband waits 175 s before it starts sending transmit data to the RF2968 (to allow the synthesizer to settle). the device can- not be in both transmit and receive modes at the same time, so rxen must be low to enter this mode. data sync a transition on bdata1 (0 to 1) starts the synchronization of data between the RF2968 and the baseband device. enable pa the pa is powered up (pdpa=1) and ready to begin transmitting. tx data data is transmitted in this mode. (the synthesizer has settled and the data path synchronized.) disable pa the pa is powered down (pdpa=0). 1 s later, the synthesizer and the rest of the transmit circuits are powered down (pd_tx=0). this delay prevents any ?unwanted transmission? during power down. the device then returns to idle mode when the baseband writes to the control registers and drives txen low. rx pll wait this is the start of the receive sequence and is entered from idle mode when a control register write from the baseband forces rxen high. this turns on the synthesizer and starts a timer which powers up the receive path circuits after a fixed delay (pd_rx=1). the baseband device expects to receive data 175 s after the control register write. rx data received data is sent to the baseband device via bdata1 (unsynchronized) and recdata (synchronized with recclk). within this state, there are two dc estimation modes. in the ?access code? mode, the RF2968 uses a fast dc estimation to adjust for large frequency offsets. an internal timer (or alternatively bpktctl) signals the end of the sync word, placing the dc estimation circuitry in the ?payload? mode, in which compensation is made for small frequency offsets. a control register write from the baseband drives rxen low and returns the device to idle mode. this turns off the receive path (pd_rx=0) and the synthesizer.
preliminary 11-135 RF2968 rev a13 010912 11 transceivers state machine the RF2968 state machine is clocked with a 1mhz signal which is derived from the reference oscillator. (the mark - space ratio of this 1mhz clock and its precise frequency are not important.) the inputs and outputs for all the states are summarized in the table below. table 1. state machine inputs and outputs notes: a. when the inputs try to force the controller into an undefined or illegal state, the state machine will remain in its present state (e.g., if the present state is idle and the inputs try to force the device to tx data, the chip will stay in idle mode). b. pd_tx goes high after a fixed delay following txen going high. c. 1 s delay from the pd_pa going low to pd_tx going low. d. pd_rx goes high after a fixed delay following rxen going high. e. bpktctl must be low to distinguish data sync from enable pa. f. if rxen=1 when entering idle from disable pa, then idle is held for 1 s, after which the state transitions to rx pll wait. inputs outputs previous state present state a bnpwr bxtlen bdata1 bpktctl rxen txen pdxtal clrb pdtx pdpa pdrx x off 0xxxxx00000 off pwron wait 1 0 1 x x x 1 1 0 0 0 pwronwaitholdxtl 1 1 1 x 00 1 1000 hold xtl idle 1 1 x x 0 0 1 1 0 0 0 idle sleep 1 0 x x 00 0 1000 sleep wait xtl 1 1 x x 0 0 1 1 0 0 0 wait xtl idle 1 1 x x 00 1 1000 idle wait data sync 1 1 x 0 e 01 1 1 1 b 00 wait data data sync 1 1 x 0 e x1 1 1100 data sync enable pa 1 1 x 1 x 1 1 1 1 1 0 enablepa txdata 1 1 x 1 x1 1 1110 tx data disable pa 1 1 x 0 x 1 1 1 0 c 00 disable pa idle 1 1 x x x f 0 1 1000 idle rx pll wait 1 1 x x 1 0 1 1 0 0 1 d rx pll wait rx data 1 1 x x 1 0 1 1 0 0 1 rxdata idle 1 1 x x 0x 1 1000
preliminary 11-136 RF2968 rev a13 010912 11 transceivers special modes of operation calibration whentheRF2968is reset (clrb=0), all calibration values are cleared. therefore, after the RF2968 is powered up from the off state, it must be instructed to perform its self-calibration. circuits requiring calibration include the rx vari- able gain amplifier (vga), tx and rx pll?s, rx channel filter, rx data paths, and tx gaussian filter. calibration instructions are sent from the baseband to the RF2968 via the serial port (addressing registers 5 and 7) and must be performed in the order shown in the table below. after a calibration instruction is sent, the baseband must delay for the length of time indicated before sending the next calibration instruction; this allows time for the RF2968 circuits to settle and execute the instruction. at initialization, bypasssm, pu_xtal, pu_mult, and tx_en are set high and remain so for the duration of the calibration. register 7 is only addressed during initialization to set tx_en and configure the reference frequency and rf pll frequency. . notes: a) shaded cells indicate no change from previous state. b) set according to reference frequency. c) set rf pll frequency to a valid frequency (lo=2403 to 2481mhz). d) register 5 may be programmed immediately after register 7. transmitter test mode: during normal tx mode, the transmitter's if pll is opened for modulation of the current controlled oscillator (ico) for a short period of time (0.4 to 3ms). for development purposes, open-loop modulation may be performed for an indefinite period of time by externally supplying the required ico control voltage. this allows the ico to maintain a locked condi- tion. transmitter test mode utilizes the lpo pin, which is switched to the output of the internal loop filter of the transmitter?s if ico when set_tx_pll_lf_ext (register 7, bit 15) is set high and the 3.2khz/32khz low power oscillator is not in use. this pin may be used either to monitor the control voltage during a packet transmission or to externally supply the control voltage for an extended or continuous transmission. when monitoring the ico control voltage, the voltage on the lpo pin will drift from its initial voltage as the transmission time increases, but should remain in the range of 0.7v to 0.9v. when supplying the ico control voltage, the voltage to be applied to the lpo pin should be equal to the initial voltage measured when monitoring. bit settings for calibration sequence a calibration steps register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 required time (usec) initialization of pll 7 0 0 0 0 x b x b x b 10 x c x c x c x c x c x c x c 0 d initialization of chip control 5 1000000011000000 2500 calibrate k o of tx and rx if pll?s 5 1 0 0 0 01 0 0 1 1 0 0 0 0 0 0 1024 calibrate gaussian tx and rx vga 5 1 0 0 0101 0 1 1 0 0 01 01 285 calibrate if filters 5 1 0 0 00 00 0 1 11 0 0 1 0 1608 calibrate rx offsets 5 1 0 0 0 0 0 0 0 1 101 0 1 00 64 return chip control to state machine 50 0 0 0 0 0 0 000 00 00 0 00 total calibration time: 4481

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